The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2023

Filed:

Mar. 01, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Yang Lee, Taipei, TW;

Chih-Shan Chen, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/30 (2006.01); H01L 27/08 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01); H01L 21/3065 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/0262 (2013.01); H01L 21/02521 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/3065 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.


Find Patent Forward Citations

Loading…