The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Jul. 08, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Brandon C. Marin, Chandler, AZ (US);

Tarek Ibrahim, Mesa, AZ (US);

Srinivas Pietambaram, Chandler, AZ (US);

Andrew J. Brown, Gilbert, AZ (US);

Gang Duan, Chandler, AZ (US);

Jeremy Ecton, Gilbert, AZ (US);

Sheng C. Li, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/16 (2006.01); H01L 23/00 (2006.01); H01F 27/40 (2006.01); H05K 3/40 (2006.01); H05K 3/28 (2006.01);
U.S. Cl.
CPC ...
H05K 1/165 (2013.01); H01F 27/40 (2013.01); H01L 24/16 (2013.01); H05K 1/112 (2013.01); H05K 3/28 (2013.01); H05K 3/4007 (2013.01); H05K 3/4038 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01);
Abstract

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.


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