The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2023
Filed:
Jul. 05, 2021
University of Electronic Science and Technology of China, Chengdu, CN;
Ping Li, Chengdu, CN;
Yongbo Liao, Chengdu, CN;
Xianghe Zeng, Chengdu, CN;
Yaosen Li, Chengdu, CN;
Ke Feng, Chengdu, CN;
Chenxi Peng, Chengdu, CN;
Zhaoxi Hu, Chengdu, CN;
Fan Lin, Chengdu, CN;
Xuanlin Xiong, Chengdu, CN;
Tao He, Chengdu, CN;
University of Electronic Science and Technology of China, Chengdu, CN;
Abstract
A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.