The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2023

Filed:

Mar. 25, 2021
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Yung-Shun Chang, Kaohsiung, TW;

Chih-Pin Hung, Kaohsiung, TW;

Teck-Chong Lee, Kaohsiung, TW;

Chih-Yi Huang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4857 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/544 (2013.01); H01L 24/08 (2013.01); H01L 25/0655 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/08235 (2013.01);
Abstract

An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.


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