The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Nov. 19, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ya-Yi Tsai, Hsinchu, TW;

Chun-Liang Lai, Hsinchu, TW;

Shu-Yuan Ku, Hsinchu County, TW;

Ryan Chia-Jen Chen, Chiayi, TW;

Ming-Ching Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/3213 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/31122 (2013.01); H01L 21/32135 (2013.01); H01L 21/32136 (2013.01); H01L 21/32137 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/66545 (2013.01); H01L 21/0274 (2013.01); H01L 21/31053 (2013.01); H01L 21/32139 (2013.01);
Abstract

A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.


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