The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Sep. 08, 2021
Applicant:

Chengdu Monolithic Power Systems Co., Ltd., Chengdu, CN;

Inventors:

Yingjiang Pu, Chengdu, CN;

Hunt Hang Jiang, Saratoga, CA (US);

Xiuhong Guo, Chengdu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/3157 (2013.01); H01L 23/53209 (2013.01); H01L 25/0655 (2013.01); H01L 23/53257 (2013.01); H01L 24/80 (2013.01);
Abstract

An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.


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