The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Jan. 04, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Winnie Victoria Wei-Ning Chen, Zhubei, TW;

Meng-Hsuan Hsiao, Hsinchu, TW;

Tung-Ying Lee, Hsinchu, TW;

Pang-Yen Tsai, Jhu-bei, TW;

Yasutoshi Okuno, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/02636 (2013.01); H01L 21/30625 (2013.01); H01L 21/823807 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/1033 (2013.01); H01L 29/16 (2013.01); H01L 29/42392 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.


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