The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

Feb. 12, 2020
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Arun Virupaksha Gowda, Rexford, NY (US);

Paul Alan McConnelee, Albany, NY (US);

Shakti Singh Chauhan, Niskayuna, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/34 (2006.01); H01L 23/538 (2006.01); H05K 3/30 (2006.01); H05K 3/46 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/48 (2006.01); H01L 25/10 (2006.01); H01L 23/42 (2006.01); H01L 23/433 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 3/36 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/34 (2013.01); H01L 23/367 (2013.01); H01L 23/373 (2013.01); H01L 23/481 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/27 (2013.01); H01L 24/43 (2013.01); H01L 24/46 (2013.01); H01L 24/82 (2013.01); H01L 24/83 (2013.01); H01L 25/105 (2013.01); H05K 3/305 (2013.01); H05K 3/4602 (2013.01); H01L 23/42 (2013.01); H01L 23/433 (2013.01); H01L 24/45 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/2402 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/2711 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32501 (2013.01); H01L 2224/43 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/46 (2013.01); H01L 2224/80365 (2013.01); H01L 2224/85399 (2013.01); H01L 2224/92144 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/207 (2013.01); H05K 1/0206 (2013.01); H05K 1/0209 (2013.01); H05K 1/183 (2013.01); H05K 1/185 (2013.01); H05K 3/301 (2013.01); H05K 3/306 (2013.01); H05K 3/366 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/09845 (2013.01); H05K 2203/302 (2013.01); Y02P 70/50 (2015.11);
Abstract

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.


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