The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2023

Filed:

May. 20, 2021
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Yung-Feng Lin, Taoyuan, TW;

Su-Chueh Lo, Hsingchu, TW;

Teng-Hao Yeh, Zhubei, TW;

Hang-Ting Lue, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.


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