The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2023

Filed:

Nov. 21, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Bo Xu, Wuhan, CN;

Ping Yan, Wuhan, CN;

Chuan Yang, Wuhan, CN;

Jing Gao, Wuhan, CN;

Zongliang Huo, Wuhan, CN;

Lu Zhang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/11582 (2017.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/11565 (2017.01); H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 27/11565 (2013.01); H01L 29/1037 (2013.01); H01L 21/0228 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 29/518 (2013.01);
Abstract

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.


Find Patent Forward Citations

Loading…