The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2023
Filed:
Oct. 07, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Inventors:
Yen-Cheng Liu, New Taipei, TW;
Cheng-Yu Hsieh, Hsinchu, TW;
Shang-Ying Tsai, Taoyuan County, TW;
Kuei-Sung Chang, Kaohsiung, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/02 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/02 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0264 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/012 (2013.01); B81B 2207/07 (2013.01); B81B 2207/096 (2013.01); B81C 1/0023 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/036 (2013.01); B81C 2203/037 (2013.01); B81C 2203/0792 (2013.01);
Abstract
A method of manufacturing a semiconductive structure includes receiving a first substrate; disposing an interconnection layer on the first substrate; forming a plurality of conductors over the interconnection layer; filing gaps between the plurality of conductors with a film; forming a barrier layer over the film; removing the barrier layer; and partially removing the film to expose a portion of the interconnection and leave a portion of the interconnection layer covered by the film.