The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2023

Filed:

Nov. 11, 2020
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Hsiu-Mei Yu, Hsinchu, TW;

Cheng-Yi Hsieh, Hsinchu County, TW;

Wei-Chan Chang, Taoyuan, TW;

Chang-Sheng Lin, Miaoli County, TW;

Chun-Yi Wu, Taichung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 23/14 (2006.01); H01L 27/088 (2006.01); H01L 23/488 (2006.01); H01L 29/417 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42372 (2013.01); H01L 23/14 (2013.01); H01L 23/488 (2013.01); H01L 23/53242 (2013.01); H01L 27/088 (2013.01); H01L 29/41725 (2013.01);
Abstract

A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.


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