The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Aug. 12, 2020
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Hao Che Feng, Kaohsiung, TW;

Hung Jen Huang, Tainan, TW;

Hsin Min Han, Kaohsiung, TW;

Shih-Wei Su, Tainan, TW;

Ming Shu Chiu, Tainan, TW;

Pi-Hung Chuang, Changhua County, TW;

Wei-Hao Huang, New Taipei, TW;

Shao-Wei Wang, Taichung, TW;

Ping Wei Huang, Pingtung County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7854 (2013.01); H01L 21/0217 (2013.01); H01L 21/02247 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 29/0649 (2013.01); H01L 29/66818 (2013.01);
Abstract

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.


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