The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Jun. 01, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kazuki Isozumi, Kuwana, JP;

Parth Amin, Fremont, CA (US);

Sayako Nagamine, Yokkaichi, JP;

Anubhav Khandelwal, San Jose, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 29/52 (2006.01); G11C 16/08 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 29/12 (2013.01); G11C 29/52 (2013.01);
Abstract

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.


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Isozumi, Kazuki. (2023). System and methods for programming nonvolatile memory having partial select gate drains (U.S. Patent No. 11581049). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11581049

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