The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Sep. 24, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

James Fitzpatrick, Laguna Niguel, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Patrick Robert Khayat, San Diego, CA (US);

AbdelHakim S. Alhussien, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/10 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5004 (2013.01);
Abstract

A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.


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