The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Aug. 20, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Jui Hsu, Taichung, TW;

Ying-Fu Tung, Taichung, TW;

Chun-Sheng Lu, Taichung, TW;

Kuo-Feng Huang, Taichung, TW;

Yu-Chi Kuo, Taichung, TW;

Wang-Ta Li, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 27/11524 (2013.01); H01L 29/66825 (2013.01);
Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.


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