The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2023
Filed:
Nov. 18, 2021
Intel Corporation, Santa Clara, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Narayan Srinivasa, Portland, OR (US);
Feng Chen, Shanghai, CN;
Joydeep Ray, Folsom, CA (US);
Ben J. Ashbaugh, Folsom, CA (US);
Nicolas C. Galoppo Von Borries, Portland, OR (US);
Eriko Nurvitadhi, Hillsboro, OR (US);
Balaji Vembu, Folsom, CA (US);
Tsung-Han Lin, Campbell, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Rajkishore Barik, Santa Clara, CA (US);
Sara S. Baghsorkhi, San Jose, CA (US);
Justin E. Gottschlich, Santa Clara, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Nadathur Rajagopalan Satish, Santa Clara, CA (US);
Farshad Akhbari, Chandler, AZ (US);
Dukhwan Kim, San Jose, CA (US);
Wenyin Fu, Folsom, CA (US);
Travis T. Schluessler, Hillsboro, OR (US);
Josh B. Mastronarde, Sacramento, CA (US);
Linda L. Hurd, Cool, CA (US);
John H. Feit, Folsom, CA (US);
Jeffery S. Boles, Folsom, CA (US);
Adam T. Lake, Portland, OR (US);
Karthik Vaidyanathan, Berkeley, CA (US);
Devan Burke, Portland, OR (US);
Subramaniam Maiyuran, Gold River, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.