The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Mar. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Zhi-Chang Lin, Zhubei, TW;

Wei-Hao Wu, Hsinchu, TW;

Jia-Ni Yu, New Taipei, TW;

Huan-Chieh Su, Tianzhong Township, TW;

Ting-Hung Hsu, MiaoLi, TW;

Chih-Hao Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/311 (2006.01); H01L 21/8238 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/31144 (2013.01); H01L 21/76843 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/4232 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 21/823437 (2013.01);
Abstract

A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.


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