The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Dec. 21, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chong Zhang, Chandler, AZ (US);

Cheng Xu, Chandler, AZ (US);

Junnan Zhao, Gilbert, AZ (US);

Ying Wang, Chandler, AZ (US);

Meizi Jiao, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/16 (2006.01); H01L 23/538 (2006.01); H01L 49/02 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/568 (2013.01); H01L 23/49811 (2013.01); H01L 23/528 (2013.01); H01L 23/5386 (2013.01); H01L 28/40 (2013.01); H01L 2224/1623 (2013.01); H01L 2224/16265 (2013.01);
Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.


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