The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Dec. 31, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mukta Ghate Farooq, Hopewell Junction, NY (US);

Katsuyuki Sakuma, Fishkill, NY (US);

Krishna R. Tunga, Wappingers Falls, NY (US);

Hilton T. Toy, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4853 (2013.01); H01L 21/4882 (2013.01); H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 23/3675 (2013.01); H01L 23/3737 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/35121 (2013.01);
Abstract

A lidded chip package apparatus has reduced latent thermal stress in an under-chip high-CTE layer of the chip package because the lid of the package was adhered to a substrate of the package and cured during a same thermal excursion as when underfill was dispensed and cured under a chip of the package, and the chip package was cooled from the combined underfill and lidding process to room temperature with the lid adhered to the chip and the substrate, thereby reducing latent thermal stress in the under-chip high-CTE layer of the chip package.


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