The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2022
Filed:
Dec. 23, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Zhicheng Ding, Shanghai, CN;
Yong She, Songjiang, CN;
Bin Liu, Shanghai, CN;
Aiping Tan, Shanghai, CN;
Li Deng, Shanghai, CN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/42 (2013.01); H01L 24/49 (2013.01); H01L 25/065 (2013.01); H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01);
Abstract
A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.