The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Feb. 18, 2020
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Chia-Wen Wang, Tainan, TW;

Chien-Hung Chen, Hsinchu, TW;

Chia-Hui Huang, Tainan, TW;

Jen Yang Hsueh, Tainan, TW;

Ling Hsiu Chou, Tainan, TW;

Chih-Yang Hsu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/11521 (2017.01); H01L 29/51 (2006.01); H01L 29/788 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); G11C 16/16 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); H01L 21/76224 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.


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