The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Jan. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Tien Tung, Hsinchu, TW;

Szu-Wei Huang, Hsinchu, TW;

Zhi-Ren Xiao, Hsinchu, TW;

Yin-Chuan Chuang, Hsinchu, TW;

Yung-Chien Huang, Hsinchu, TW;

Kuan-Ting Liu, Hsinchu, TW;

Tzer-Min Shen, Hsinchu, TW;

Chung-Wei Wu, Hsin-Chu County, TW;

Zhiqiang Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/3205 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/32053 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.


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