The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

May. 11, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kamal M. Karda, Boise, ID (US);

Deepak Chandra Pandey, Uttarakhand, IN;

Haitao Liu, Boise, ID (US);

Richard J. Hill, Boise, ID (US);

Guangyu Huang, Boise, ID (US);

Yunfei Gao, Boise, ID (US);

Ramanathan Gandhi, Boise, ID (US);

Scott E. Sills, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/267 (2006.01); H01L 29/786 (2006.01); H01L 27/108 (2006.01); H01L 29/207 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/267 (2013.01); H01L 27/10805 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/207 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01);
Abstract

Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.


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