The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Sep. 28, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jack T. Kavalieros, Portland, OR (US);

Ian A. Young, Portland, OR (US);

Ram Krishnamurthy, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Gregory Chen, Portland, OR (US);

Hui Jae Yoo, Portland, OR (US);

Van H. Le, Portland, OR (US);

Abhishek Sharma, Hillsboro, OR (US);

Raghavan Kumar, Hillsboro, OR (US);

Huichu Liu, Santa Clara, CA (US);

Phil Knag, Hillsboro, OR (US);

Huseyin Sumbul, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); G11C 13/0021 (2013.01); H01L 27/2436 (2013.01); H01L 29/517 (2013.01); H01L 45/16 (2013.01);
Abstract

A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.


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