The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2022
Filed:
Apr. 13, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 23/64 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01); H01L 23/50 (2006.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H01L 23/642 (2013.01); H01L 23/49816 (2013.01); H01L 23/50 (2013.01); H05K 1/0231 (2013.01); H05K 1/181 (2013.01); H01L 23/13 (2013.01); H01L 23/49833 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/1053 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10734 (2013.01); H05K 2201/2018 (2013.01);
Abstract
A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.