The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

May. 19, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Indira Seshadri, Niskayuna, NY (US);

Ekmini Anuja De Silva, Slingerlands, NY (US);

Jing Guo, Niskayuna, NY (US);

Ruqiang Bao, Niskayuna, NY (US);

Muthumanickam Sankarapandian, Niskayuna, NY (US);

Nelson Felix, Slingerlands, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/823412 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01);
Abstract

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.


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