The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Nov. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Ching Wang, Kinmen County, TW;

Wen-Hsing Hsieh, Hsinchu, TW;

Jon-Hsu Ho, New Taipei, TW;

Wen-Yuan Chen, Taoyuan County, TW;

Chia-Ying Su, Hsinchu, TW;

Chung-Wei Wu, Hsinchu County, TW;

Zhiqiang Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0615 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/1608 (2013.01); H01L 29/42376 (2013.01);
Abstract

Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.


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