The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2022
Filed:
Jun. 24, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Fang Chen, Hsinchu, TW;
Kuo-Chiang Ting, Hsinchu, TW;
Jhon Jhy Liaw, Zhudong Township, TW;
Min-Chang Liang, Zhu-Dong Town, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/11582 (2017.01); H01L 49/02 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823821 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0886 (2013.01); H01L 27/1116 (2013.01); H01L 27/11582 (2013.01); H01L 28/00 (2013.01);
Abstract
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.