The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Jul. 22, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Pochun Wang, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Chih-Ming Lai, Hsinchu, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Jung-Chan Yang, Longtan Township, TW;

Ru-Gun Liu, Zhubie, TW;

Ya-Chi Chou, Hsinchu, TW;

Yi-Hsiung Lin, Zhubei, TW;

Yu-Xuan Huang, Hsinchu, TW;

Yu-Jung Chang, Hsinchu, TW;

Guo-Huei Wu, Hsinchu, TW;

Shih-Ming Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/76895 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01);
Abstract

An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.


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