The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Apr. 01, 2020
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Chun-Yi Chou, Hsinchu, TW;

Po-Hsien Cheng, Taipei, TW;

Tse-An Chen, Taoyuan, TW;

Miin-Jang Chen, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/28194 (2013.01); H01L 21/76224 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.


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