The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jan. 16, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Han Wui Then, Portland, OR (US);

Paul B. Fischer, Portland, OR (US);

Zdravko Boos, Munich, DE;

Marko Radosavljevic, Portland, OR (US);

Sansaptak Dasgupta, Hillsboro, OR (US);

Assignee:

Intel Coropration, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/20 (2006.01); H01L 23/66 (2006.01); H01P 1/205 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/20 (2013.01); H01L 23/66 (2013.01); H01L 29/2003 (2013.01); H01P 1/2053 (2013.01); H01L 2223/6677 (2013.01);
Abstract

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.


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