The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Apr. 17, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Keng-Ying Liao, Hsinchu, TW;

Huai-Jen Tung, Hsinchu, TW;

Chih Wei Sung, Hsinchu, TW;

Po-zen Chen, Hsinchu, TW;

Yu-Chien Ku, Hsinchu, TW;

Yu-Chu Lin, Hsinchu, TW;

Chi-Chung Jen, Hsinchu, TW;

Yen-Jou Wu, Hsinchu, TW;

Tsun-kai Tsao, Hsinchu, TW;

Yung-Lung Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14689 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14636 (2013.01); H01L 27/14649 (2013.01);
Abstract

A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.


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