The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Dec. 07, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chi-Che Wu, Hsinchu, TW;

Tsung-Yang Hung, Hsinchu County, TW;

Jia-Ming Guo, Hsinchu, TW;

Edna Fang, Hsinchu, TW;

Ming-Yih Wang, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/31721 (2013.01);
Abstract

A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.


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