The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Jan. 22, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Jayprakash Chipalkatti, Santa Clara, CA (US);

Zuhair Bokharey, Santa Clara, CA (US);

Don Templeton, Santa Clara, CA (US);

Brian Schieck, Santa Clara, CA (US);

Julie Lam, Santa Clara, CA (US);

Prashant Pathak, Santa Clara, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 22/14 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13027 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/14179 (2013.01); H01L 2224/8121 (2013.01); H01L 2224/81143 (2013.01); H01L 2924/014 (2013.01);
Abstract

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm. A ratio of a coefficient of thermal expansion of the substrate (CTE) to a coefficient of thermal expansion of the integrated circuit die (CTE) is at least about 3:1. A method of manufacturing an IC package is also disclosed.


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