The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Sep. 11, 2020
Applicant:

Amkor Technology Singapore Holding Pte. Ltd., Singapore, SG;

Inventors:

Gyu Wan Han, Incheon, KR;

Won Bae Bang, Incheon, KR;

Ju Hyung Lee, Gyeonggi-Do, KR;

Min Hwa Chang, Incheon, KR;

Dong Joo Park, Gyeonggi-do, KR;

Jin Young Khim, Seoul, KR;

Jae Yun Kim, Incheon, KR;

Se Hwan Hong, Seoul, KR;

Seung Jae Yu, Incheon, KR;

Shaun Bowers, Gilbert, AZ (US);

Gi Tae Lim, Incheon, KR;

Byoung Woo Cho, Seoul, KR;

Myung Jea Choi, Incheon, KR;

Seul Bee Lee, Gyeonggi-Do, KR;

Sang Goo Kang, Seoul, KR;

Kyung Rok Park, Incheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/13 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 25/18 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/568 (2013.01); H01L 23/3185 (2013.01); H01L 23/49816 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48157 (2013.01); H01L 2224/85005 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01);
Abstract

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.


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