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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11495494 B1

PDFFull Text
Date of Patent:
Nov. 08, 2022

Filed:

Nov. 19, 2019

Methods for reducing contact depth variation in semiconductor fabrication

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yun Lee, Taipei County, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Yi-Jyun Huang, New Taipei, TW;

Sheng-Hsiung Wang, Hsinchu County, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Hsin Yi Hsieh

Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/76805 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/535 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.

Find Patent Forward Citations

Lee, Yun. (2022). Methods for reducing contact depth variation in semiconductor fabrication (U.S. Patent No. 11495494). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11495494

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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