The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Dec. 09, 2020
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Ching-Yang Wen, Pingtung County, TW;

Li Wang, Singapore, SG;

Kai Cheng, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/41725 (2013.01); H01L 29/66484 (2013.01); H01L 29/7831 (2013.01);
Abstract

A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.


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