The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Jan. 05, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Joydeep Ray, Folsom, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Pattabhiraman K, Bangalore, IN;

Balaji Vembu, Folsom, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Niranjan L. Cooray, Folsom, CA (US);

Josh B. Mastronarde, Sacramento, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06F 9/455 (2018.01); G06T 1/60 (2006.01); G09G 5/36 (2006.01); G09G 5/00 (2006.01); G09G 5/393 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06T 15/04 (2011.01); G06T 15/80 (2011.01); G06T 17/10 (2006.01); G06T 17/20 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06F 9/45504 (2013.01); G06F 9/45558 (2013.01); G06F 9/4806 (2013.01); G06F 9/5011 (2013.01); G06T 1/60 (2013.01); G09G 5/001 (2013.01); G09G 5/363 (2013.01); G09G 5/393 (2013.01); G06F 9/5016 (2013.01); G06F 9/5044 (2013.01); G06F 2009/45583 (2013.01); G06T 15/04 (2013.01); G06T 15/80 (2013.01); G06T 17/10 (2013.01); G06T 17/20 (2013.01); G09G 2360/08 (2013.01); G09G 2360/10 (2013.01); G09G 2360/121 (2013.01); G09G 2360/122 (2013.01); G09G 2360/125 (2013.01);
Abstract

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.


Find Patent Forward Citations

Loading…