The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Nov. 16, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Tsung-Yu Chiang, New Taipei, TW;

Kuang-Hsin Chen, Jung-Li, TW;

Hsin-Lung Chao, Hsinchu, TW;

Chen Chu-Hsuan, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 23/544 (2006.01); H01L 21/8234 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/3085 (2013.01); H01L 21/76224 (2013.01); H01L 23/544 (2013.01); H01L 27/0886 (2013.01); H01L 29/1033 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.


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