The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jan. 21, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Nicholas R. Tapias, Boise, ID (US);

Sanjeev Sapra, Boise, ID (US);

Anish A. Khandekar, Boise, ID (US);

Shen Hu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); H01L 21/02381 (2013.01); H01L 21/02428 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01);
Abstract

Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.


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