The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Oct. 21, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Bau-Ming Wang, Kaohsiung, TW;

Che-Fu Chiu, New Taipei, TW;

Chun-Feng Nieh, Hsinchu, TW;

Huicheng Chang, Tainan, TW;

Yee-Chia Yeo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/74 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 21/02532 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/28088 (2013.01); H01L 21/74 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/0847 (2013.01); H01L 29/1054 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. The semiconductor substrate includes a first semiconductor material. Implanting the dopants may be performed at a temperature in a range of 150° C. to 500° C. The channel layer may include a second semiconductor material. The channel layer may be doped with dopants of the first conductivity type.


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