The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2022
Filed:
Feb. 26, 2020
Applicants:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc Nanjing Company, Limited, Nanjing, CN;
Inventors:
Assignees:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC NANJING COMPANY, LIMITED, Nanjing, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 21/288 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76807 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/2885 (2013.01); H01L 21/28568 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76873 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H01L 23/53228 (2013.01);
Abstract
A method of making a dual damascene interconnect includes operations of depositing a metal hardmask over a dielectric layer; etching a metal hardmask opening in the metal hardmask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer, to expose a top surface of a base conductive layer; modifying a sidewall of the metal hardmask opening; and depositing a conductive material in the metal hardmask opening and the at least one interconnect opening.