The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Feb. 23, 2021
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc China Company, Limited, Songjiang, CN;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

XiuLi Yang, Hsinchu, TW;

Ching-Wei Wu, Hsinchu, TW;

He-Zhou Wan, Hsinchu, TW;

Kuan Cheng, Hsinchu, TW;

Luping Kong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 8/10 (2006.01); G11C 8/08 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.


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