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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11444082 B1

PDFFull Text
Date of Patent:
Sep. 13, 2022

Filed:

Sep. 30, 2020

Semiconductor apparatus having stacked gates and method of manufacture thereof

Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Jeffrey Smith, Clifton Park, NY (US);

Anton J. deVilliers, Clifton Park, NY (US);

Kandabara N. Tapily, Mechanicville, NY (US);

Subhadeep Kal, Albany, NY (US);

Gerrit J. Leusink, Rexford, NY (US);

Assignee:

Tokyo Electron Limited, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Tong-Ho Kim

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 21/822 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/02603 (2013.01); H01L 21/28088 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 27/0688 (2013.01); H01L 27/124 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/78696 (2013.01); H01L 21/823871 (2013.01);
Abstract

Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

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