The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Nov. 22, 2021
Applicant:

Deca Technologies Usa, Inc., Tempe, AZ (US);

Inventors:

Clifford Sandstrom, Richfield, MN (US);

Benedict San Jose, Metro Manila, PH;

Timothy L. Olson, Phoenix, AZ (US);

Craig Bishop, Scottsdale, AZ (US);

Assignee:

Deca Technologies USA, Inc., Tempe, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/211 (2013.01); H01L 2224/215 (2013.01);
Abstract

A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.


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