The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2022
Filed:
Feb. 18, 2020
Applicant:
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Inventors:
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/03 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/03827 (2013.01); H01L 2224/10145 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11827 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/81007 (2013.01); H01L 2224/81232 (2013.01);
Abstract
Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.