The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Jan. 03, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Hsuan Hsiao, Hsinchu, TW;

Winnie Victoria Wei-Ning Chen, Zhubei, TW;

Tung Ying Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/165 (2013.01); H01L 29/66742 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01);
Abstract

Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.


Find Patent Forward Citations

Loading…