The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Aug. 03, 2020
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Tzu-Hung Lin, Zhubei, TW;

Chia-Cheng Chang, Hsinchu, TW;

I-Hsuan Peng, Hsinchu, TW;

Nai-Wei Liu, Kaohsiung, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 23/043 (2006.01); H01L 23/13 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/043 (2013.01); H01L 23/13 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 23/5385 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.


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