The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Mar. 06, 2019
Applicant:

Novellus Systems, Inc., Fremont, CA (US);

Inventors:

Anand Chandrashekar, Fremont, CA (US);

Esther Jeng, Los Altos, CA (US);

Raashina Humayun, Los Altos, CA (US);

Michal Danek, Cupertino, CA (US);

Juwen Gao, San Jose, CA (US);

Deqi Wang, San Jose, CA (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/108 (2006.01); C23C 16/04 (2006.01); C23C 16/06 (2006.01); H01L 21/285 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); C23C 16/04 (2013.01); C23C 16/045 (2013.01); C23C 16/06 (2013.01); H01L 21/28556 (2013.01); H01L 21/321 (2013.01); H01L 21/76898 (2013.01); H01L 27/10891 (2013.01);
Abstract

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.


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